Digital analog converter for the extraction of test signals from mixed integrated circuits

Abstract

The construction of integrated circuits involves testing the correct operation of its internal blocks. For this, a common practice is the integration of functional blocks to stimulate the internal subsystems and extract the responses to those stimuli. In this article, the design and simulation of a circuit for the extraction of the response signals of the devices under test in analog and mixed-signal integrated circuits is presented. The extraction block is a 2-stage 5-bit segmented A/D converter, operating at a sampling frequency of 10 MHz, implemented in a 0.12 µm technological process, which can be powered with 1.5 Vdc. This proposal offers a reduction in the area consumed, by requiring fewer comparators than other similar solutions found in the literature.